Monthly Archives: August 2013

Prefer isunknown over unary xor equals

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Stuart Sutherland and Don Mills have a good introduction to using SystemVerilog Assertions [1]. Unfortunately they like checking for unknown signals with the construct ^value !== 1'bx. I disagree with this construct. It is easy to forget the 1 in 1'bx, mistake 1'bx as equivalent to 'bx – which it is not – or mistype the construct so that the assertion becomes useless. It is far better to use !$isunknown(value). This construct is safer and immediately conveys the intent. The only drawback is that it costs two extra characters over Stuart and Don’s construct.

I have personally mistyped ^value !== 1'bx enough times to drop it completely in favor of !$isunknown(value).

[1] SystemVerilog Assertions Are For Design Engineers Too!

Mapping between MMR addresses and UVM registers

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Using logical names instead of hard coded addresses is an advantage for any software development – including verification. That doesn’t mean that logical names are always better than addresses. Some times an address is handy and other times I would really have wished for the register name. Fortunately UVM has methods to convert from one to another:

function uvm_reg_addr_t uvm_reg::get_address(uvm_reg_map map = null)
function uvm_reg_addr_t uvm_mem::get_address(uvm_reg_addr_t offset = 0, uvm_reg_map map = null)
function uvm_reg uvm_reg_map::get_reg_by_offset(uvm_reg_addr_t offset, bit read = 1)

Example one-liners:

uvm_reg_addr_t addr;
uvm_reg rg;
uvm_mem mem;
addr = regmodel0.MY_BLOCK0.MY_REG0.get_address();
addr = regmodel0.MY_BLOCK0.MY_MEM0.get_address(addr);
rg = regmodel0.default_map.get_reg_by_offset(addr);
mem = regmodel0.default_map.get_mem_by_offset(addr);

Note that the UVM Register Layer allows a register to span multiple addresses.