Stuart Sutherland and Don Mills have a good introduction to using SystemVerilog Assertions [1]. Unfortunately they like checking for unknown signals with the construct ^value !== 1'bx. I disagree with this construct. It is easy to forget the 1 in 1'bx, mistake 1'bx as equivalent to 'bx – which it is not – or mistype the construct so that the assertion becomes useless. It is far better to use !$isunknown(value). This construct is safer and immediately conveys the intent. The only drawback is that it costs two extra characters over Stuart and Don’s construct.
I have personally mistyped ^value !== 1'bx enough times to drop it completely in favor of !$isunknown(value).