I have noticed that the university server which hosts my thesis has disappeared from the internet, thus making my thesis unavailable. I have also noticed that this thesis has 8 citations, so in the interest of preserving history, I am making it available again below. This thesis is a decade old, so newer research is most likely much better, but section 2 and 3.1 still have some value.
Abstract
There has been renewed interest in a number system for integrated circuits
called decimal floating-point. There are inherent problems in today’s binary
floating-point numbers that require financial computations to be performed
in software which is 100-1000 times slower than a hardware based equivalent.
For example adding a 5% tax to a $0.70 phone call will round off wrongly in
binary floating-point.
With the increase in transistor count surpassing the increase in clock
speed on modern computer processors, manufacturers are looking into new
strategies for speeding up computations including the financial ones and a
commercial processor with decimal floating-point already exists. Despite the
interest, the problems of decimal arithmetic slower and requiring more area
than binary remain.
This thesis explores the possibility of combining binary and decimal
floating-point units thereby saving area without sacrificing too much speed.
In the course of this investigation a novel decimal fused multiply-add (FMA)
based floating-point unit is developed and combined with a known binary
FMA algorithm. This FMA primarily uses known components, but one major
component – the decimal leading one predictor – is new.
Synthesis results show that the latencies for the binary and decimal paths
are comparable to current solutions, but the area used is much larger than the
individual units.
In order to make the FMA fulfill the goals of this thesis, further research
should look into reducing area in the FMA. Before the area is reduced
significantly, it is not recommended to use a combined binary and decimal
floating-point unit.