Gate array ECO standard cells are a relatively new phenomenon which haven’t gotten much attention in the world of Digital RTL Design. They are pretty neat in that you can change a filler or decap cell to a different standard cell by changing only the metallization of a chip that is the masks for the back-end-of-line of chip production. This reduces cost and time to market for a respin. With mask costs reaching multi-million dollars for a single tape-out this means that you can easily save a million dollars through the help of gate level arrays.
Mask programmable ROMs are similar to gate level arrays in that you only need to change the metallazation of an existing chip to enable new functionality. The change is usually limited to just a via layer between two metal layers in order to keep costs at a minumum.
The insight here is that you can get same benefit of having a mask programmable ROM by using gate level arrays without having to source an externally developed metal programmable ROM or build a custom one yourself. Also, you will not need special BIST or production test requirements that you will have to spend engineering time on handling before tapeout. The downside is that the gate array standard cell is twice the size of a normal standard cell and probably larger than a single bit cell of a metal mask programmable ROM. Also, you will probably have to change metal1 and the contact layer which increases cost for a new mask set compared to the classical ROM version.
Pros
- No external sourcing
- No custom ROM development
- No BIST or special product test requirement
Cons
- Higher area
- Higher metal mask cost if you need to change anything
How to create your own metal mask programmable ROM
Pick two gate array cells – one inverter and one buffer – of the same size and your standard N-input mux and stick a the correct gate array buffer or inverter output onto the input of N-input mux. Tie the inputs of gate array cells to zero or to the output of a flop (for example for test or debug purposes). You can also optimize this by combining the first stage of the mux with the buffer/inverter by using a nand2/nor2 gate array pair. You will need to fiddle around a little with some truth tables to make it work out. There are a couple of possible combinations one of which may work better for your specific case, so you may have to play with it a little.