SystemVerilog Assertions (SVAs) are effective for low level verification. UVM is effective for high level verification. Unfortunalely, the high level concerns cloud my critical thinking and I forget what low level issues that I should be concerned about. Fortunately, many SVAs are mostly mechanical applications of a few simple concepts. I have listed my checklist for SVAs when writing RTL below. I look at it for inspiration when I feel that I should add another assertion.
| Item | Comments |
|---|---|
| Registers and outputs on reset | |
| No unknown control signals | Input and Output |
| No unknown data in transactions | Input and Output |
| Restricted data ranges | F. x. address ranges – math functions – data relationships |
| Restricted enumerations | Enum and control signal combinations |
| Valid handshake protocols | Every interface – spurious ack – cause has effect – data stable |
| Time | Clock periods – setup/hold time – glitches – CDC – rate control |
| Invariants | Data integrity – overflow/underflow – FSM transitions |
The first assertions in the list are the easiest to write. The last ones are the hardest to write.