The standard library for SystemVerilog is tiny and inadequate. Fortunately, the industry has improved the state of the world a little. Below is a curated list of libraries for SystemVerilog design and verification.

Design

• OH! Open Hardware for Chip Designers A kitchen sink of RTL code. The common area is the most interesting part. Other parts are very application specific. MIT License

Verification

• UVM The state of the art verification framework for simulation. The killer feature is the register layer. Replaces VMM and OVM. You want to be using this. Apache License
• svlib String and file handling functions that SystemVerilog is missing. Also Regular expressions and YAML parsing. Apache License
• ClueLib String handling and collections. Also some networking related methods. MIT License
• OVL The forerunner to SystemVerilog Assertions. A bit dated today. Apache License
• SVUnit Unit testing for your testbench code. Apache License.
• SVAUnit Unit testing for your SystemVerilog Assertions.  Apache License.